Intel’s latest Hi-k 45nm processor 25
The 45 nanometer (45 nm) routine is the subsequent miracle (commercially viable as of Nov 2007) in semiconductor fabrication. Intel proposed mass producing 45 nm chips in Nov 2007, AMD is targeting 45 nm prolongation in 2008, whilst IBM, Infineon, Samsung, as well as Chartered Semiconductor have already finished the usual 45 nm routine platform. By the finish of 2008, SMIC will be the initial China-based semiconductor association to pierce to 45 nm, carrying protected the bulk 45 nm routine from IBM. At IEDM 2007, some-more technical sum of Intel's 45 nm routine were revealed: * 160 nm embankment representation (73% of 65 nm generation) * 35 nm embankment length (same as 65 nm generation) * 1 nm homogeneous oxide thickness, with 7 Å passing from one to another covering * gate-last routine regulating manikin polysilicon * 9 layers of low-k Cu interconnect, the final being the thick "redistribution" covering * contacts made some-more similar to rectangles than circles for internal interconnection * lead-free wrapping * 1.36 ma/um nfet expostulate stream * 1.07 ma/um pfet expostulate current, 51% faster than 65 nm generation, with aloft hole mobility due to enlarge from 23% to 30% Ge in embedded sige stressors Intel's 45nm processor website: www.intel.com
